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" white electronic designs #$%& footprint compatible with wed3c7558m-xbx and wed3c750a8m-200bx footprint compatible with motorola mpc 745 the wedc 755e/ssram multichip package is tar- geted for high performance, space sensitive, low power systems and supports the following power management features: doze, nap, sleep and dynamic power management. the WED3C755E8M-XBX multichip package con- sists of: ? 755 risc processor (e die revision) dedicated 1mb ssram l2 cache, configured as 128kx72 21mmx25mm, 255 ceramic ball grid array (cbga) core frequency/l2 cache frequency (300mhz/ 150mhz, 350mhz/175mhz) maximum 60x bus frequency = 66mhz the WED3C755E8M-XBX is offered in commercial (0c to +70c), industrial (-40c to +85c) and mili- tary (-55c to +125c) temperature ranges and is well suited for embedded applications such as mis- siles, aerospace, flight computers, fire control sys- tems and rugged critical systems. *this data sheet describes a product that is subject to change without notice. e ' ()* white electronic designs ! " white electronic designs l2pin_data l2pin_data l2pin_data l2pin_data l2 clk_out a l2we l2ce a 0-16 l2clk_out b l2pin_data l2pin_data l2pin_data l2pin_data l2zz p 755 dqa dqb dqc dqd k sgw se1 sa 0-16 sa 0-16 sgw se1 k dqa dqb dqc dqd ssram 1 ssram 2 ft sbd sbc sbb sba sw adsp adv se2 adsc se3 lbo g ft sbd sbc sbb sba sw adsp adv se2 adsc se3 lbo g l20vdd l20vdd l2dp0-3 dp0-3 l2dp4-7 dp0-3 zz zz u2 u1 e l2 cache ssram u2 l2 cache ssram u1 stdo stdi stms stck tdi tdo 755 tms tck trst e ' ()* white electronic designs ball assignments of the 255 cbga package as viewed from the top surface. side profile of the cbga package to indicate the direction of the top surface view. ! " white electronic designs c16, e4, d13, f2, d14, g1, d15, e2, d16, d4, e13, g2, e15, h1, e16, h2, f13, j1, f14, high i/o ovdd a[0-31] j2, f15, h3, f16, f4, g13, k1, g15, k2, h16, m1, j15, p1 aack l2 low input ovdd abb k4 low i / o ovdd ap[0-3] c1, b4, b3, b2 high i/o ovdd artry j4 low i/o ovdd avdd a10 ? ? 2.0v bg l1 low input ovdd br b6 low output ovdd bvsel (4, 5, 6) b1 high input ovdd ci e1 low output ovdd ckstp_in d8 low input ovdd ckstp_out a6 low ouput ovdd clk_out d7 ? output ovdd dbb j14 low i/o ovdd dbg n1 low input ovdd dbdis h15 low input ovdd dbwo g4 low input ovdd p14, t16, r15, t15, r13, r12, p11, n11, r11, t12, t11, r10, p9, n9, t10, r9, t9, p8, high i/o ovdd dh[0-31] n8, r8, t8, n7, r7, t7, p6, n6, r6, t6, r5, n5, t5, t4 k13, k15, k16, l16, l15, l13, l14, m16, m15, m13, n16, n15, n13, n14, p16, p15, high i/o ovdd dl[0-31] r16, r14, t14, n10, p13, n12, t13, p3, n3, n4, r3, t1, t2, p4, t3, r4 dp[0-7] m2, l3, n2, l4, r1, p2, m4, r2 high i/o ovdd drtry g16 low input ovdd gbl f1 low i/o ovdd gnd c5, c12, e3, e6, e8, e9, e11, e14, f5, f7, f10, f12, g6, g8, g9, g11, h5, h7, h10, h12, ? ? gnd j5, j7, j10, j12, k6, k8, k9, k11, l5, l7, l10, l12, m3, m6, m8, m9, m11, m14, p5, p12 hreset a7 low input ovdd int b15 low input ovdd l1_tstclk (1) d11 high input ? l2_tstclk (1) d12 high input ? l2avdd (8) l11 ? ? 2.0v l2ovdd e10, e12, m12, g12, g14, k12, k14 ? ? l20vdd l2vsel (4, 5, 6, 7) b5 high input l20vdd lssd_mode (1) b10 low input ? mcp c13 low input ovdd nc (no-connect) c3, c6, d5, d6, h4, a4, a5, a2, a3 ? ? ? ovdd (2) c7, e5, g3, g5, k3, k5, p7, p10, e7, m5, m7, m10 ? ? ovdd pll_cfg[0-3] a8, b9, a9, d9 high input ovdd qack d3 low input ovdd qreq j3 low output ovdd rsrv d1 low output ovdd smi a16 low input ovdd sreset b14 low input ovdd stck (9) b7 ? input l20vdd stdi c8 ? input l20vdd stdo j16 ? output l20vdd ' ()* white electronic designs ! stms (10) b8 ? input l2ov dd sysclk c9 ? input ov dd ta h14 low input ov dd tben c2 high input ov dd tbst a14 low i/o ov dd tck c11 high input ov dd tdi (6) a11 high input ov dd tdo a12 high output ov dd tea h13 low input ov dd tlbisync c4 low input ov dd tms (6) b11 high input ov dd trst (6) c10 low input ov dd ts j13 low i/o ov dd tsiz[0-2] a13, d10, b12 high output ov dd tt[0-4] b13, a15, b16, c14, c15 high i/o ov dd wt d2 low output ov dd vdd (2) f6, f8, f9, f11, g7, g10, h6, h8, h9, h11, j6, j8, j9, j11, k7, k10, l6, l8, l9 ? ? 2.0v voldet (3) f3 ? output ? " notes: 1. these are test signals for factory use only and must be pulled up to ov dd for normal machine operation. 2. ov dd inputs supply power to the i/o drivers and vdd inputs supply power to the processor core. 3. internally tied to gnd in the bga package to indicate to the power supply that a low-voltage processor is present. this signa l is not a power supply pin. 4. to allow processor bus i/0 voltage changes, provide the option to connect bvsel and l2vsel independently to either ov dd or to gnd . 5. uses one of 15 existing no-connects in wedc?s wed3c750a8m-200bx. 6. internal pull up on die. 7. ov dd supplies power to the processor bus, jtag, and all control signals except the l2 cache controls (l2ce, l2we, and l2zz); l2ov dd supplies power to the l2 cache i/o interface (l2addr (0-16], l2data (0-63), l2dp{0-7] and l2sync-out) and the l2 control signals and the ssram power supplies; and vdd supplies power to the processor core and the pll and dll (after filtering to become av dd and l2av dd respectively). this column serves as a reference for the nominal voltage supported on a given signal as selected by the bvsel/l2vsel pin configurations and the voltag e supplied. for actual recommended value of vin or supply voltages see recommended operating conditions table. 8. uses one of 20 existing vdd pins in wedc's wed3c750a8m-200bx, no board level design changes are necessary. for new designs of WED3C755E8M-XBX refer to pll power supply filtering. 9. to disable ssram tap controllers without interfering with the normal operation of the devices, stck should be tied low (gnd) to prevent clocking the devices. 10. stdi and stms are internally pulled up and may be left unconnected. upon power-up the ssram devices will come up in a reset state which will not interfere with the operation of the device. ! " white electronic designs core supply voltage vdd -0.3 to 2.5 v (4) pll supply voltage avdd -0.3 to 2.5 v (4) l2 dll supply voltage l2avdd -0.3 to 2.5 v (4) 60x bus supply voltage ovdd -0.3 to 3.6 v (3) l2 bus supply voltage l2ovdd -0.3 to 3.6 v (3) input supply processor bus vin -0.3 to 0vdd +0.3 v (2) l2 bus vin -0.3 to l20vdd +0.3 v (2) jtag signals vin -0.3 to 3.6 v (2) storage temperature range tstg -55 to 150 c # $ %& & core supply voltage vdd 2.0 100mv v pll supply voltage avdd 2.0 100mv v l2 dll supply voltage l2avdd 2.0 100mv v processor bus supply 2.5 125mv v voltage (2) 3.3 165mv v l2 bus supply voltage (3) l2vsel = 1 l20vdd 3.3 165mv v input voltage processor bus vin gnd to ovdd v jtag signals vin gnd to ovdd v notes: 1. functional and tested operating conditions are given in operating conditions table. absolute maximum ratings are stress rati ngs only, and functional operation at the maximums is not guaranteed. stresses beyond those listed may affect device reliability or cause per manent damage to the device. 2. vin must not exceed ovdd by more than 0.3v at any time including during power-on reset. 3. ovdd/l2ovdd must not exceed vdd/avdd/l2avdd by more than 1.6 v at any time including during power-on reset. 4. vdd/avdd/l2avdd must not exceed l2ovdd/ovdd by more than 0.4 v at any time including during power-on reset. &&"" ' " note: (1) these are the recommended and tested operating conditions. proper device operation outside of these conditions is not guar anteed (2) bvsel = 0 is not available (3) l2vsel = 0 is not available bvsel = 1 ovdd ' ()* white electronic designs !! "#!$%& #! "'#$%& full-on mode t ypical 4.1 4.6 w 1, 3 maximum 6.7 7.9 w 1, 2 doze mode maximum 2.5 2.8 w 1, 2 nap mode maximum 1700 1800 mw 1, 2 sleep mode maximum 1200 1300 mw 1, 2 sleep mode?pll and dll disabled maximum 500 500 mw 1, 2 (' & "" "" "" " " ) notes: 1. these values apply for all valid 60x bus and l2 bus ratios. the values do not include ovdd; avdd and l2avdd suppling power. o vdd power is system dependent, but is typically <10% of vdd power. worst case power consumption, for avdd=15mw and l2avdd=15mw. 2. maximum power is measured at vdd=2.1v while running an entirely cache-resident, contrived sequence of instructions which keep the execution units maximally busy. 3. typical power is an average value measured at vdd=avdd=l2avdd=2.0v, ovdd=l2ovdd=3.3v in a system, executing typical applicati ons and benchmark sequences. the l2 cache control register, shown in figure 5, is a supervisor-level, implementation-specific spr used to configure and operate the l2 cache. it is cleared by hard reset or power-on reset. * '$ ' the l2cr bits are described in table 1. * '$ ' l2e l2siz l2clk l2ram l2i l20h 0 0 l2ctr 0 1 2 3 4 6 7 8 9 10 111213141516 17 1819 20212223 24 30 31 l2pe l2do l2ctl l2ts l2sl l 2byp l2io l2dro l2ip l2wt l2df l2cs reserved ( ) *$ junction to ambient (no airflow) theta ja 14.2 11.2 c/w 1 junction to ball theta jb 8.6 5.7 c/w 1 junction to case (t op) theta jc 0.1 0.1 c/w 1 note 1: refer to pbga thermal resistance correlation at www.whiteedc.com in the application notes section for modeling conditi ons *'&$ ! " white electronic designs #$ # 0 l2e l2 enable. enables l2 cache operation (including snooping) starting with the next transaction the l2 cache unit receives. before enabling the l2 cache, the l2 clock must be configured through l2cr[2clk], and the l2 dll must stabilize. all other l2cr bits must be set appropriately. the l2 cache may need to be invalidated globally. 1 l2pe l2 data parity checking enable. enables parity generation and checking for the l2 data ram interface. when disabled, gener ated parity is always zeros. l2 parity is supported by wedc?s WED3C755E8M-XBX, but is dependent on application. 2?3 l2siz l2 size?should be set according to the size of the l2 data rams used. +++& ,- . ("/ 001&-%#% 4?6 l2clk l2 clock ratio (core-to-l2 frequency divider). specifies the clock divider ratio based from the core clock frequency that the l2 data ram interface is to operate at. when these bits are cleared, the l2 clock is stopped and the on-chip dll for the l2 interface is disabled. for nonzero values, the processor generates the l2 clock and the on-chip dll is enabled. after the l2 cl ock ratio is chosen, the dll must stabilize before the l2 interface can be enabled. the resulting l2 clock frequency cannot be slow er than the clock frequency of the 60x bus interface. 000 l2 clock and dll disabled 001 1 010 1.5 011 reserved +22 3 101 2.5 110 3 111 reserved 7?8 l2ram l2 ram type?configures the l2 ram interface for the type of synchronous srams used: pipelined (register-register) synchronous burst srams that clock addresses in and clock data out the 755 does not burst data into the l2 cache, it generates an address for each access. +2 4 5 6- 6!6,7 66 '&- . ("/ 001&-%#% 9 l2do l2 data only. setting this bit enables data-only operation in the l2 cache. for this operation, instruction transactions from the l1 instruction cache already cached in the l2 cache can hit in the l2, but new instruction transactions from the l1 instruction cache are trea ted as cache-inhibited (bypass l2 cache, no l2 checking done). when both l2do adn l2io are set, the l2 cache is effectively locked (ca che misses do not cause new entries to be allocated but write hits use the l2). 10 l2i l2 global invalidate. setting l2i invalidates the l2 cache globally by clearing the l2 status bits. this bit must not be s et while the l2 cache is enabled. see motorola?s user manual for l2 invalidation procedure. 11 l2ctl l2 ram control (zz enable). setting l2ctl enables the automatic operation of the l2zz (low-power mode) signal for cache rams. sleep mode is supported by the ("/ 001&-%#%8 while l2ctl is asserted, l2zz asserts automatically when the device enters nap or sleep mode and negates automatically when the device exits nap or sleep mode. this bit should not be set when the device is in nap mode and snooping is to be performed through deassertion of qack. 12 l2wt l2 write-through. setting l2wt selects write-through mode (rather than the default write-back mode) so all writes to the l2 cache also write through to the system bus. for these writes, the l2 cache entry is always marked as exclusive rather than modified. this bit mu st never be asserted after the l2 cache has been enabled as previously-modified lines can get remarked as exclusive during normal op eration. 13 l2ts l2 test support. setting l2ts causes cache block pushes from the l1 data cache that result from 5. and 56 instructions to be written only into the l2 cache and marked valid, rather than being written only to the system bus and marked invalid in the l2 cache in case of hit. this bit allows a 595. instruction sequence to be used with the l1 cache enabled to easily initialize the l2 cache with any address and data information. this bit also keeps 59 instructions from being broadcast on the system and single-beat cacheable store misses in the l2 from being written to the system bus. 2: . 7$3 6644 67 6 665. 668 14?15 l2oh l2 output hold. these bits configure output hold time for address, data, and control signals driven to the l2 data rams. 22:$6* 5 - . ("/ 001&-%#% ' ()* white electronic designs # 16 l2sl l2 dll slow. setting l2sl increases the delay of each tap of the dll delay line. it is intended to increase the delay through the dll to accommodate slower l2 ram bus frequencies. 2: . ("/ 001&-%#% because l2 ram interface is operated above 100 mhz. 17 l2df l2 di fferential clock. this mode supports the differential clock requirements of late-write srams. 2: . ("/ 001&-%#% because late-write srams are not used. 18 l2byp l2 dll bypass is reserved. 2: . ("/ 001&-%#% 19-20 ? reserved. these bits are implemented but not used; keep at 0 for future compatibility. 21 l2io l2 instruction-only. setting this bit enables instruction-only operation in the l2 cache. for this operation, data transactions fr om the l1 data cache already cached in the l2 cache can hit in the l2 (including writes), but new data transactions (transactions that miss in the l 2) from the l1 data cashe are treated as cache-inhibited (bypass l2 cache, no l2 checking done). when both l2do and l2io are set, the l2 cache is e ffectively locked (cache misses do not cause new entries to be allocated but write hits use the l2). note that this bit can be programmed dynamically. 22 l2cs l2 clock stop. setting this bit causes the l2 clocks to the srams to automatically stop whenever the mpc755 enters nap or sleep mo des, and automatically restart when exiting those modes (including for snooping during nap mode). it operates by asynchronously gating o ff the l2clk_out [a:b] signals while in nap or sleep mode. the l2sync_out/sync_in path remains in operation, keeping the dll synchroni zed. this bit is provided as a power-saving alternative to the l2ctl bit and its corresponding zz pin, which may not be useful for dynami c stopping/ restarting of the l2 interface from nap and sleep modes due to the relatively long recovery time from zz negation that the sram requires. 23 l2dro l2 dll rollover. setting this bit enables a potential rollover (or actual rollover) condition of the dll to cause a checkstop for the processor. a potential rollover condition occurs when the dll is selecting the last tap of the delay line, and thus may risk rolling over to the first tap with one adjustment while in the process of keeping synchronized. such a condition is improper operation for the dll, and, while thi s condition is not expected, it allows detection for added security. this bit can be set when the dll is first enabled (set with the l2clk bit s) to detect rollover during initial synchronization. it could also be set when the l2 cache is enabled (with l2e bit) after the dll has ach ieved its initial lock. 24?30 l2ctr l2 dll counter (read-only). these bits indicate the current value of the dll counter (0 to 127). they are asynchronously r ead when the l2cr is read, and as such should be read at least twice with the same value in case the value is asynchronously caught in transition. t hese bits are intended to provide observability of where in the 128-bit delay chain the dll is at any given time. generally, the dll operatio n should be considered at risk if it is found to be within a couple of taps of its beginning or end point (tap 0 or tap 128). 31 l2ip l2 global invalidate in progress (read only)?see the motorola user?s manual for l2 invalidation procedure. #$ ! " white electronic designs the av dd and l2av dd power signals are provided on the WED3C755E8M-XBX to provide power to the clock gen- eration phase-locked loop and l2 cache delay-locked loop respectively. to ensure stability of the internal clock, the power supplied to the av dd input signal should be filtered of any noise in the 500khz to 10 mhz resonant frequency range of the pll. a circuit similar to the one shown in figure 6 using surface mount capacitors with minimum effective series inductance (esl) is recommended. multiple small capacitors of equal value are recommended over a single large value capacitor. the circuit should be placed as close as possible to the av dd pin to minimize noise coupled from nearby circuits. an identical but separate circuit should be placed as close as possible to the l2av dd pin. it is often possible to route directly from the capacitors to the av dd pin, which is on the periphery of the 255 bga footprint, without the inductance of vias. the l2av dd pin may be more difficult to route but is proportionately less critical. ! " the wed3 c755e8m-xbx requires pull-up resistors (1 kw-5 kw) on several control pins of the bus interface to maintain the control signals in the negated state after they have been actively negated and released by the processor or other bus masters. these pins are ts, abb, aack, artry, dbb, dbwo, ta, tea, and dbdis. drtry should also be connected to a pull-up resistor (1 kw-5 kw) if it will be used by the system; otherwise, this signal should be connected to hreset to select no-drtry mode. three test pins also require pull-up resistors (100 w-1 kw). these pins are l1_tstclk, l2_tstclk, and lssd_mode. these signals are for factory use only and must be pulled up to ovdd for normal machine operation. in addition, ckstp_out is an open-drain style output that re- quires a pull-up resistor (1 kw-5 kw) if it is used by the system. during inactive periods on the bus, the address and transfer attributes may not be driven by any master and may, therefore, float in the high-impedance state for relatively long periods of time. since the processor must co ntinually monitor these sig- nals for snooping, this float condition may cause additional power draw by the input receivers on the processor or by other receivers in the system. these signals can be pulled up through weak (10 kw) pull-up resistors by the system or may be otherwise driven by the system during inactive periods of the bus to avoid this additional power draw, but address bus pull-up resistors are not neccessary for proper device opera- tion. the snooped address and transfer attribute inputs are: a[0:31], ap[0:3], tt[0:4], tbst, and gbl. the data bus input receivers are normally turned off when no read operation is in progress and, therefore, do not require pull-up resistors on the bus. other data bus receiv- ers in the system, however, may require pull-ups, or that those signals be otherwise driven by the system during inactive periods by the system. the data bus signals are: dh[0:31], dl[0:31], and dp[0:7]. if 32-bit data bus mode is selected, the input receivers of the unused data and parity bits will be disabled, and their outputs will drive logic zeros when they would otherwise normally be driven. for this mode, these pins do not re- quire pull-up resistors, and should be left unconnected by the system to minimize possible output switching. if address or data parity is not used by the system, and the respective parity checking is disabled through hid0, the input receivers for those pins are disabled, and those pins do not require pull-up resistors and should be left uncon- nected by the system. if all parity generation is disabled through hid0, then all parity checking should also be dis- abled through hid0, and all parity pins may be left uncon- nected by the system. avdd (or l2avdd) 2.2 f 2.2 f gnd low esl surface mount capacitors vdd 10 ? ' ()* white electronic designs package outline 21x25mm interconnects 255 (16x16 ball array less one) pitch 1.27mm maximum module height 3. 90mm ball diameter 0.8mm & $$ '" ''; ' notes: 1. dimensions in millimeters and paranthetically in inches. 2. a1 corner is designated with a ball missing the array. t r p n m l k j h g f e d c b a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 bottom view top view ! " white electronic designs +,( '##,-$ ./. (,0,1*(,2 *3*1,45,2 ! 6,,7,5$%& ""#$% #$& ' ""#$%#$& ' *%,(, 0452 ( )* +! 8 ? 2 , - ././0 + 1 23 4 9$ 40%0 *3*1, 98 ? +%04,, ,460(, 01 6: '"' '& powerpc is a trademark of international business machine corp. ' ()* white electronic designs !"# $#%! 56 5 & ' '-5 78 !&$'$ "($'# )* ;< % ( + 1 + - ( 9 + 1 ' 8 2583:;: 4 9 ( " 9 3+ 1 / "3"< = / / 3< = / = =- 78 - 83 3! / < .0 1( / /&< .0 1( /+ >- 8 ,( + 1 ' 8 2583: :4 " 9 3!,' + ,( -8 3!+ 1 # -8 |
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